RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,176 commits
1,231 contributors

Rank

196 1

Started

2006-06-02 6,972 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 144 commits #366 26 contributors #280
Past 90 days 390 commits #440 54 contributors #258
Past 365 days 1,548 commits #493 177 contributors #219
Past 1095 days 7,001 commits #374 449 contributors #209
All time 25,176 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
805 Robert Foss
0 0 0 0 1
805 Samuel Martin
0 0 0 0 1
805 Sean Cross
0 0 0 0 1
805 Sean Cross
0 0 0 0 1
805 Sergey Alirzaev
0 0 0 0 1
805 Sinan Lin
0 0 0 0 1
805 Stafford Horne
0 0 0 0 1
805 Stef O'Rear
0 0 0 0 1
805 Stephan Linz
0 0 0 0 1
805 Takahiro Mozilla
0 0 0 0 1
805 Theodore A. Roth
0 0 0 0 1
805 Tilman Sauerbeck
0 0 0 0 1
805 Tim Kryger
0 0 0 0 1
805 Tobias Klauser Isovalent
0 0 0 0 1
805 Vianney le Clément de Saint-Marcq
0 0 0 0 1
805 Vijai Kumar K
0 0 0 0 1
805 Viktar Palstsiuk
0 0 0 0 1
805 Vincent Palatin
0 0 0 0 1
805 Vivien Didelot
0 0 0 0 1
805 Wim Lewis
0 0 0 0 1
Showing 881 to 900 of 1231 results
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Contributing Companies

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