RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Rank

209 19

Started

2006-06-02 6,858 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent

GitHub Stars

8,179 #1,437

Weekly commits since inception

2006 2015 2025

Weekly contributors since inception

2006 2015 2025

Recent Project Activity

Past 30 days 86 commits #633 29 contributors #263
Past 90 days 279 commits #583 65 contributors #205
Past 365 days 1,719 commits #450 197 contributors #186
Past 1095 days 6,959 commits #380 452 contributors #202
All time 25,673 commits 1,234 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
817 anpilog 0 0 0 0 1
817 Anton Kuzmin 0 0 0 0 1
817 Andrew 0 0 0 0 1
817 Ash Charles 0 0 0 0 1
817 Atish Patra 0 0 0 0 1
817 Ulrich-Lorenz Schlüter 0 0 0 0 1
817 Bartosz Bielawski 0 0 0 0 1
817 B. A. Bryce 0 0 0 0 1
817 Bernhard Kiesbauer 0 0 0 0 1
817 Bernhard Rosenkränzer 0 0 0 0 1
817 bluew 0 0 0 0 1
817 Jörg Mische 0 0 0 0 1
817 Stephane Bonnet 0 0 0 0 1
817 Boran Car 0 0 0 0 1
817 Bradey Honsinger 0 0 0 0 1
817 Bruce Ableidinger 0 0 0 0 1
817 Bruno FLEURETTE 0 0 0 0 1
817 Byron Kubert 0 0 0 0 1
817 Chris Casinghino 0 0 0 0 1
817 Cheng-Shiun Tsai 0 0 0 0 1
Showing 901 to 920 of 1234 results Previous Next
Contributing Companies

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