OSS Project

RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Rank
237
Decreased by 43
Started
2006-06-02 6,752 days ago
Open Core Products
Open Core Company Product
efabless efabless
SiFive SiFive Core IP
Tenstorrent Grayskull
Ventana Micro Systems Ventana
GitHub Stars
7,886 #1,432
Stackoverflow Questions with tag riscv
1,411 #440
Weekly commits since inception
2006 2015 2024
Weekly contributors since inception
2006 2015 2024
Recent Project Activity
Day Span Commits Contributors
30 65 #719 25 #292
90 301 #563 56 #254
365 1,987 #396 192 #195
1095 7,063 #377 436 #216
All time 25,198 1,195
Contributing Individuals
Commits past X days
Contributor 30 90 All
786 Sean Cross 0 0 1
786 Sean Cross 0 0 1
786 Sergey Alirzaev 0 0 1
786 Stafford Horne 0 0 1
786 Stef O'Rear 0 0 1
786 Stephan Linz 0 0 1
786 Takahiro 0 0 1
786 Theodore A. Roth 0 0 1
786 Tilman Sauerbeck 0 0 1
786 Tim Kryger 0 0 1
786 Tobias Klauser 0 0 1
786 Vianney le Clément de Saint-Marcq 0 0 1
786 Vijai Kumar K 0 0 1
786 Viktar Palstsiuk 0 0 1
786 Vincent Palatin 0 0 1
786 Vivien Didelot 0 0 1
786 Wesley Terpstra 0 0 1
786 Wim Lewis 0 0 1
786 Xi Wang 0 0 1
786 Zachary T Welch 0 0 1
Contributing Companies

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