RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Rank

214 26

Started

2006-06-02 6,857 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent

GitHub Stars

8,179 #1,437

Weekly commits since inception

2006 2015 2025

Weekly contributors since inception

2006 2015 2025

Recent Project Activity

Past 30 days 85 commits #630 28 contributors #273
Past 90 days 284 commits #580 64 contributors #210
Past 365 days 1,721 commits #448 197 contributors #187
Past 1095 days 6,959 commits #380 452 contributors #202
All time 25,671 commits 1,234 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
817 Jan Dakinevich 0 0 0 0 1
817 Joshua Wise 0 0 0 0 1
817 Jussi Kivilinna 0 0 0 0 1
817 Linus Walleij 0 0 0 0 1
817 Luc Maranget 0 0 0 0 1
817 Lucas 0 0 0 0 1
817 Mara Bos 0 0 0 0 1
817 Marc Reilly 0 0 0 0 1
817 Mark Vels 0 0 0 0 1
817 Marti Bolivar 0 0 0 0 1
817 Masaki Muranaka 0 0 0 0 1
817 Matt Reimer 0 0 0 0 1
817 Mehmet Oguz Derin 0 0 0 0 1
817 Michael Clark 0 0 0 0 1
817 Michael Grzeschik 0 0 0 0 1
817 Michael Hunold 0 0 0 0 1
817 Mickaël 0 0 0 0 1
817 Ngo Iok Ui 0 0 0 0 1
817 Oleksandr Kozaruk 0 0 0 0 1
817 Olivier DANET 0 0 0 0 1
Showing 861 to 880 of 1234 results Previous Next
Contributing Companies

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