RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,179 commits
1,231 contributors

Rank

195 1

Started

2006-06-02 6,972 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 147 commits #360 26 contributors #283
Past 90 days 395 commits #433 54 contributors #257
Past 365 days 1,541 commits #500 178 contributors #215
Past 1095 days 7,008 commits #374 450 contributors #206
All time 25,179 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
805 Chris Johns
0 0 0 0 1
805 Chris Morgan
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805 Cornelius Diekmann
0 0 0 0 1
805 Dan Robertson
0 0 0 0 1
805 Daniel Kucera refurbed
0 0 0 0 1
805 Georg Sauthoff
0 0 0 0 1
805 Hsiangkai Wang
0 0 0 0 1
805 Icenowy Zheng
0 0 0 0 1
805 Jacob Rosenthal
0 0 0 0 1
805 Jan Dakinevich
0 0 0 0 1
805 Joshua Wise
0 0 0 0 1
805 Jussi Kivilinna
0 0 0 0 1
805 Linus Walleij
0 0 0 0 1
805 Luc Maranget
0 0 0 0 1
805 Lucas
0 0 0 0 1
805 Mara Bos Fusion Engineering
0 0 0 0 1
805 Marc Reilly
0 0 0 0 1
805 Mark Vels
0 0 0 0 1
805 Marti Bolivar
0 0 0 0 1
805 Masaki Muranaka
0 0 0 0 1
Showing 841 to 860 of 1231 results
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Contributing Companies

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