RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,267 commits
1,238 contributors

Rank

212 10

Started

2006-06-02 6,999 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 85 commits #585 28 contributors #254
Past 90 days 376 commits #449 58 contributors #240
Past 365 days 1,492 commits #510 173 contributors #225
Past 1095 days 7,023 commits #370 447 contributors #209
All time 25,267 commits 1,238 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
806 Mark Vels
0 0 0 0 1
806 Marti Bolivar
0 0 0 0 1
806 Masaki Muranaka
0 0 0 0 1
806 Matt Reimer
0 0 0 0 1
806 Mehmet Oguz Derin
0 0 0 0 1
806 Michael Clark
0 0 0 0 1
806 Michael Grzeschik
0 0 0 0 1
806 Michael Hunold
0 0 0 0 1
806 Mickaël
0 0 0 0 1
806 Ngo Iok Ui
0 0 0 0 1
806 Oleksandr Kozaruk
0 0 0 0 1
806 Olivier DANET
0 0 0 0 1
806 Olof Kindgren Qamcom
0 0 0 0 1
806 Paolo Bonzini RedHat (IBM)
0 0 0 0 1
806 Peter Griffin
0 0 0 0 1
806 Peter Korsgaard Barco
0 0 0 0 1
806 Rabeeh Khoury
0 0 0 0 1
806 Radek Dostal
0 0 0 0 1
806 Reto Schneider
0 0 0 0 1
806 Richard Braun
0 0 0 0 1
Showing 861 to 880 of 1238 results
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Contributing Companies

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