RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,270 commits
1,238 contributors

Rank

214 10

Started

2006-06-02 7,000 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 85 commits #586 28 contributors #252
Past 90 days 376 commits #451 58 contributors #242
Past 365 days 1,492 commits #510 173 contributors #225
Past 1095 days 7,023 commits #370 447 contributors #209
All time 25,270 commits 1,238 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
806 Richard Purdie
0 0 0 0 1
806 Richard Watts
0 0 0 0 1
806 Richard Xia
0 0 0 0 1
806 Robert Foss
0 0 0 0 1
806 Samuel Martin
0 0 0 0 1
806 Sean Cross
0 0 0 0 1
806 Sean Cross
0 0 0 0 1
806 Sergey Alirzaev
0 0 0 0 1
806 Sinan Lin
0 0 0 0 1
806 Stafford Horne
0 0 0 0 1
806 Stef O'Rear
0 0 0 0 1
806 Stephan Linz
0 0 0 0 1
806 Takahiro Mozilla
0 0 0 0 1
806 Theodore A. Roth
0 0 0 0 1
806 Tilman Sauerbeck
0 0 0 0 1
806 Tim Kryger
0 0 0 0 1
806 Tobias Klauser Isovalent
0 0 0 0 1
806 Vianney le Clément de Saint-Marcq
0 0 0 0 1
806 Vijai Kumar K
0 0 0 0 1
806 Viktar Palstsiuk
0 0 0 0 1
Showing 881 to 900 of 1238 results
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Contributing Companies

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