RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,261 commits
1,238 contributors

Rank

214 15

Started

2006-06-02 6,998 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 83 commits #602 27 contributors #267
Past 90 days 372 commits #454 59 contributors #239
Past 365 days 1,492 commits #511 175 contributors #222
Past 1095 days 7,024 commits #370 447 contributors #210
All time 25,261 commits 1,238 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
806 Ash Charles
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806 Brian Brooks
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806 Brian Campbell
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806 Chris Johns
0 0 0 0 1
806 Chris Morgan
0 0 0 0 1
806 Cornelius Diekmann
0 0 0 0 1
806 Dan Robertson
0 0 0 0 1
806 Daniel Kucera refurbed
0 0 0 0 1
806 Georg Sauthoff
0 0 0 0 1
806 Hsiangkai Wang
0 0 0 0 1
806 Icenowy Zheng
0 0 0 0 1
806 Jacob Rosenthal
0 0 0 0 1
806 Jan Dakinevich
0 0 0 0 1
806 Joshua Wise
0 0 0 0 1
806 Jussi Kivilinna
0 0 0 0 1
806 Linus Walleij
0 0 0 0 1
806 Luc Maranget
0 0 0 0 1
806 Lucas
0 0 0 0 1
806 Mara Bos Fusion Engineering
0 0 0 0 1
806 Marc Reilly
0 0 0 0 1
Showing 841 to 860 of 1238 results
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Contributing Companies

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