RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,257 commits
1,238 contributors

Rank

220 23

Started

2006-06-02 6,997 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 80 commits #630 26 contributors #279
Past 90 days 371 commits #455 59 contributors #239
Past 365 days 1,490 commits #512 175 contributors #222
Past 1095 days 7,021 commits #370 447 contributors #210
All time 25,257 commits 1,238 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
806 Andrea Merello
0 0 0 0 1
806 Andreas Bomholtz
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806 Andreas Kemnade
0 0 0 0 1
806 Jeremy Bennett
0 0 0 0 1
806 Jerome Lambourg
0 0 0 0 1
806 Jerry Shih
0 0 0 0 1
806 Greg Ungerer
0 0 0 0 1
806 Grigori Goronzy
0 0 0 0 1
806 Eugeniy Meshcheryakov
0 0 0 0 1
806 Felix Ruess
0 0 0 0 1
806 Felix Yan
0 0 0 0 1
806 Diego Elio Pettenò Meta / Facebook
0 0 0 0 1
806 Ed Maste
0 0 0 0 1
806 Erik Botö
0 0 0 0 1
806 Craig Blackmore
0 0 0 0 1
806 Ben Gardiner
0 0 0 0 1
806 Bill Traynor
0 0 0 0 1
806 Bjarne Steinsbo
0 0 0 0 1
806 Angus Ainslie
0 0 0 0 1
806 Arun Thomas
0 0 0 0 1
Showing 821 to 840 of 1238 results
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Contributing Companies

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