RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,257 commits
1,238 contributors

Rank

217 18

Started

2006-06-02 6,997 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 80 commits #622 26 contributors #273
Past 90 days 371 commits #453 59 contributors #239
Past 365 days 1,490 commits #511 175 contributors #223
Past 1095 days 7,021 commits #370 447 contributors #210
All time 25,257 commits 1,238 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
692 tscn92
0 0 0 0 2
692 richard vegh
0 0 0 0 2
692 Wjatscheslaw Stoljarski (Slawa)
0 0 0 0 2
692 William D. Jones
0 0 0 0 2
692 Yauheni Kaliuta
0 0 0 0 2
806 Kyle Schwarz
0 0 0 0 1
806 Laszlo Papp
0 0 0 0 1
806 Johannes Stezenbach
0 0 0 0 1
806 John David Anglin
0 0 0 0 1
806 John Rigby
0 0 0 0 1
806 John Szakmeister
0 0 0 0 1
806 Jonathan Behrens
0 0 0 0 1
806 Jonathan Tinkham
0 0 0 0 1
806 Adrien Grassein
0 0 0 0 1
806 Alberto García Hierro
0 0 0 0 1
806 Aleksander Morgado
0 0 0 0 1
806 Alexander Drozdov
0 0 0 0 1
806 Alexey Brodkin
0 0 0 0 1
806 Allen Martin
0 0 0 0 1
806 Alvin Šipraga
0 0 0 0 1
Showing 801 to 820 of 1238 results
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Contributing Companies

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