RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,937 commits
1,251 contributors

Rank

187 12

Started

2006-06-02 6,906 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 130 commits #410 30 contributors #247
Past 90 days 351 commits #533 69 contributors #204
Past 365 days 1,634 commits #464 192 contributors #199
Past 1095 days 7,003 commits #374 454 contributors #203
All time 25,937 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
711 Michele Sardo
0 0 0 0 2
711 sinan@isrc.iscas.ac.cn
0 0 0 0 2
711 Aleksey Shargalin
0 0 0 0 2
711 Jimmy
0 0 0 0 2
711 Olaf Lüke
0 0 0 0 2
711 Oleg Seiljus
0 0 0 0 2
711 Alex Crawford
0 0 0 0 2
711 Fujitsu FM3 Application Team
0 0 0 0 2
711 Owen Kirby
0 0 0 0 2
711 oyvind
0 0 0 0 2
711 Paul Richards
0 0 0 0 2
711 Peter D. Gray
0 0 0 0 2
711 Peter Dietzsch
0 0 0 0 2
711 Philip Nye
0 0 0 0 2
711 Po-wei Huang
0 0 0 0 2
711 Pushpal Sidhu
0 0 0 0 2
711 Rick Foos
0 0 0 0 2
711 Rohit Singh
0 0 0 0 2
711 Stian Skjelsad
0 0 0 0 2
711 Tomas Frydrych
0 0 0 0 2
Showing 801 to 820 of 1251 results
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Contributing Companies

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