Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Computer Architecture
started in 2015
3,752 commits
152 contributors

Rank

803 44

Git Repositories

Started

2015-04-27 3,644 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 60 commits #781 10 contributors #733
Past 90 days 382 commits #493 16 contributors #914
Past 365 days 776 commits #852 38 contributors #1,031
Past 1095 days 1,806 commits #1,174 80 contributors #1,239
All time 3,752 commits 152 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
78 Colin Schmidt
0 0 0 0 4
78 Olushola Ogunkelu
0 0 0 0 4
78 Lucheng Zhang
0 0 0 1 2
78 anniej-sifive
0 0 0 0 4
78 Vladimir Milovanović
0 0 0 1 2
78 Liu Xiaoyi
0 0 0 1 2
87 Guillaume Martres
0 0 0 1 1
87 Hongren Zheng (Zenithal)
0 0 0 1 1
87 Andrew Young
0 0 0 1 1
87 Nandor Licker
0 0 0 1 1
87 Michael Etzkorn 叶明凯
0 0 0 1 1
87 Josh Bassett
0 0 0 0 3
87 Angie Wang
0 0 0 0 3
87 Marco Origlia
0 0 0 1 1
87 Huang Rui
0 0 0 1 1
87 jensengrey
0 0 0 1 1
87 Sean Jensen-Grey
0 0 0 1 1
87 Alan L
0 0 0 1 1
87 Sihao Liu
0 0 0 1 1
87 Avimitin
0 0 0 1 1
Showing 81 to 100 of 152 results
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Contributing Companies

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