Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank

834 19

Git Repositories

chisel3

Started

2015-04-27 3,636 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Past 30 days 114 commits #510 8 contributors #914
Past 90 days 374 commits #503 15 contributors #973
Past 365 days 780 commits #857 39 contributors #1,018
Past 1095 days 1,798 commits #1,181 80 contributors #1,242
All time 3,738 commits 152 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
61 Jiuyang Liu 0 0 0 0 10
61 Tobias Jensen 0 1 1 1 1
63 Jared Barocsi 0 0 0 3 3
63 Hideto Ueno 0 0 0 3 3
65 David Biancolin 0 0 1 1 2
65 Kamyar Mohajerani 0 0 0 1 5
67 Ashe Connor 0 0 1 1 1
67 Gon Solo 0 0 0 2 2
67 Martin Erhart 0 0 1 1 1
67 Lucheng Zhang 0 0 0 2 2
67 Henry Cook 0 0 0 0 6
67 Palmer Dabbelt 0 0 0 0 6
67 Yinan Xu 0 0 0 2 2
67 Amelia Dobis 0 0 1 1 1
67 chiselbot 0 0 1 1 1
67 Alex Swehla 0 0 1 1 1
67 unlsycn 0 0 1 1 1
67 SYYANI 0 0 1 1 1
79 Fabien Marteau 0 0 0 0 4
79 Wesley Terpstra 0 0 0 0 4
Showing 61 to 80 of 152 results Previous Next
Contributing Companies

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