Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank

798 34

Git Repositories

chisel3

Started

2015-04-27 3,631 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Past 30 days 113 commits #513 9 contributors #831
Past 90 days 368 commits #511 17 contributors #890
Past 365 days 764 commits #878 40 contributors #1,003
Past 1095 days 1,782 commits #1,194 80 contributors #1,244
All time 3,717 commits 152 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
79 Stephen Twigg 0 0 0 0 4
79 Colin Schmidt 0 0 0 0 4
79 Olushola Ogunkelu 0 0 0 0 4
79 anniej-sifive 0 0 0 0 4
79 Vladimir Milovanović 0 0 0 1 2
79 Liu Xiaoyi 0 0 0 1 2
87 Guillaume Martres 0 0 0 1 1
87 Hongren Zheng (Zenithal) 0 0 0 1 1
87 Andrew Young 0 0 0 1 1
87 Nandor Licker 0 0 0 1 1
87 Michael Etzkorn 叶明凯 0 0 0 1 1
87 Josh Bassett 0 0 0 0 3
87 Angie Wang 0 0 0 0 3
87 Marco Origlia 0 0 0 1 1
87 Huang Rui 0 0 0 1 1
87 jensengrey 0 0 0 1 1
87 Sean Jensen-Grey 0 0 0 1 1
87 Alan L 0 0 0 1 1
87 Sihao Liu 0 0 0 1 1
87 Avimitin 0 0 0 1 1
Showing 81 to 100 of 152 results Previous Next
Contributing Companies

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