Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Computer Architecture
started in 2015
3,794 commits
153 contributors

Rank

933 113

Git Repositories

Started

2015-04-27 3,693 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 20 commits #1,332 8 contributors #876
Past 90 days 179 commits #819 19 contributors #771
Past 365 days 768 commits #842 39 contributors #994
Past 1095 days 1,810 commits #1,147 79 contributors #1,244
All time 3,794 commits 153 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
60 Rong Mantle Bao
0 1 1 1 1
60 Girish Pai
0 0 0 3 4
60 Tobias Jensen
0 1 1 1 1
60 jcvclouds
0 1 1 1 1
65 Jerry Zhao
0 0 1 2 2
65 Jared Barocsi
0 0 0 3 3
65 Hideto Ueno
0 0 0 3 3
65 Raffaele Meloni
0 0 0 3 3
69 David Biancolin
0 0 1 1 2
70 Martin Erhart
0 0 1 1 1
70 Henry Cook
0 0 0 0 6
70 Palmer Dabbelt
0 0 0 0 6
70 Yinan Xu
0 0 0 2 2
70 chiselbot
0 0 1 1 1
70 Alex Swehla
0 0 1 1 1
70 SYYANI
0 0 1 1 1
77 Fabien Marteau
0 0 0 0 4
77 Gon Solo
0 0 0 1 2
77 Wesley Terpstra
0 0 0 0 4
77 Stephen Twigg
0 0 0 0 4
Showing 61 to 80 of 153 results
Previous Next

Contributing Companies

Add the OSSRank badge to this project

OSSRank Badge Add this OSSRank shield to your project's README.md
[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1315)](https://ossrank.com/p/1315)