Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank

798 35

Git Repositories

chisel3

Started

2015-04-27 3,630 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Past 30 days 113 commits #512 9 contributors #829
Past 90 days 368 commits #510 17 contributors #889
Past 365 days 764 commits #878 40 contributors #1,002
Past 1095 days 1,782 commits #1,194 80 contributors #1,244
All time 3,717 commits 152 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
60 Donggyu 0 0 0 0 11
62 Jiuyang Liu 0 0 0 0 10
62 Kamyar Mohajerani 0 0 1 1 5
64 Jared Barocsi 0 0 0 3 3
64 Hideto Ueno 0 0 0 3 3
66 David Biancolin 0 0 1 1 2
67 Ashe Connor 0 0 1 1 1
67 Gon Solo 0 0 0 2 2
67 Martin Erhart 0 0 1 1 1
67 Lucheng Zhang 0 0 0 2 2
67 Henry Cook 0 0 0 0 6
67 Palmer Dabbelt 0 0 0 0 6
67 Yinan Xu 0 0 0 2 2
67 Amelia Dobis 0 0 1 1 1
67 chiselbot 0 0 1 1 1
67 Alex Swehla 0 0 1 1 1
67 unlsycn 0 0 1 1 1
67 SYYANI 0 0 1 1 1
79 Fabien Marteau 0 0 0 0 4
79 Wesley Terpstra 0 0 0 0 4
Showing 61 to 80 of 152 results Previous Next
Contributing Companies

Add this OSSRank shield to this project's README.md

[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1315)](https://ossrank.com/p/1315)