Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank

796 39

Git Repositories

chisel3

Started

2015-04-27 3,629 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Past 30 days 114 commits #513 9 contributors #825
Past 90 days 367 commits #507 17 contributors #886
Past 365 days 761 commits #883 40 contributors #999
Past 1095 days 1,784 commits #1,193 80 contributors #1,244
All time 3,714 commits 152 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
41 Albert Magyar 0 0 0 0 19
42 Robert Young 0 0 2 4 4
42 Andrew Lenharth 0 0 0 6 6
42 Hideto Ueno 0 0 2 4 4
42 Ocean Shen 0 0 1 5 5
46 jackkoenig 0 0 0 0 17
47 Jerry Zhao 0 1 2 2 2
48 Michael Maloney 0 0 2 3 3
48 jcvclouds 1 1 1 1 1
48 Benjamin Sternthal 1 1 1 1 1
48 Raffaele Meloni 0 0 2 3 3
48 Rong Mantle Bao 1 1 1 1 1
48 Tobias Jensen 1 1 1 1 1
54 colin4124 0 0 1 1 8
54 Edward Wang 0 0 0 0 13
54 edwardcwang 0 0 0 0 13
57 Boyang Han 0 0 0 0 12
57 Girish Pai 0 0 0 4 4
57 Carlos Eduardo 0 0 0 3 6
60 Abongwa Bonalais 0 0 0 1 9
Showing 41 to 60 of 152 results Previous Next
Contributing Companies

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