Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Computer Architecture
started in 2015
3,794 commits
153 contributors

Rank

928 115

Git Repositories

Started

2015-04-27 3,693 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 20 commits #1,340 8 contributors #877
Past 90 days 179 commits #819 19 contributors #771
Past 365 days 771 commits #842 40 contributors #973
Past 1095 days 1,812 commits #1,147 79 contributors #1,244
All time 3,794 commits 153 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
41 Paul Rigge
0 0 0 0 23
42 Benjamin Sternthal
0 2 2 2 2
43 Albert Magyar
0 0 0 0 19
44 Shahzaib Kashif
1 1 1 2 2
44 Robert Young
0 0 2 4 4
44 Andrew Lenharth
0 0 0 6 6
47 jackkoenig
0 0 0 0 17
48 Hideto Ueno
0 0 2 3 4
48 unlsycn
0 1 2 2 2
50 1s
1 1 1 1 1
50 Michael Maloney
0 0 2 3 3
50 Ocean Shen
0 0 0 5 5
53 Edward Wang
0 0 0 0 13
53 colin4124
0 0 1 1 8
55 Carlos Eduardo
0 0 0 3 6
55 Jason Wang
0 0 2 2 2
55 Boyang Han
0 0 0 0 12
58 Donggyu
0 0 0 0 11
58 Abongwa Bonalais
0 0 0 1 9
60 Jiuyang Liu
0 0 0 0 10
Showing 41 to 60 of 153 results
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Contributing Companies

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