Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Computer Architecture
started in 2015
3,829 commits
154 contributors

Rank

1154 123

Git Repositories

Started

2015-04-27 3,748 days ago

GitHub Stars

4,156 #1,970

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 19 commits #1,345 5 contributors #1,172
Past 90 days 56 commits #1,466 12 contributors #1,087
Past 365 days 727 commits #884 36 contributors #1,050
Past 1095 days 1,808 commits #1,140 78 contributors #1,240
All time 3,829 commits 154 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
41 Amelia Dobis
0 0 0 7 7
42 Albert Magyar
0 0 0 0 19
43 Andrew Lenharth
0 0 0 6 6
44 jackkoenig
0 0 0 0 17
45 Rong "Mantle" Bao
1 1 1 1 1
45 Robert Young
0 0 1 4 4
45 Michael Maloney
0 0 2 3 3
45 Ocean Shen
0 0 0 5 5
49 Edward Wang
0 0 0 0 13
49 Shahzaib Kashif
0 1 1 2 2
51 Boyang Han
0 0 0 0 12
51 Jason Wang
0 0 2 2 2
51 unlsycn
0 0 2 2 2
51 Benjamin Sternthal
0 0 2 2 2
55 Donggyu
0 0 0 0 11
56 colin4124
0 0 0 1 8
56 1s
0 1 1 1 1
56 Jiuyang Liu
0 0 0 0 10
56 Hideto Ueno
0 0 0 3 4
60 Jerry Zhao
0 0 1 2 2
Showing 41 to 60 of 154 results
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Contributing Companies

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