Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank

857 17

Git Repositories

chisel3

Started

2015-04-27 3,628 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Past 30 days 121 commits #490 7 contributors #1,020
Past 90 days 366 commits #506 15 contributors #970
Past 365 days 756 commits #886 38 contributors #1,049
Past 1095 days 1,778 commits #1,194 78 contributors #1,267
All time 3,707 commits 150 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
21 Fabian Schuiki 1 5 6 8 8
22 Mike Urbach 0 0 0 21 21
23 Trevor McKay 2 3 6 6 6
24 George 0 0 0 19 19
25 Albert Chen 0 0 0 17 17
26 Henry Cook
SiFive
0 0 0 0 45
27 Amelia Dobis 0 0 7 7 7
28 Martin Schoeberl 0 0 2 7 20
29 Andrew Waterman 0 0 0 0 38
30 Albert Chen 0 0 0 11 15
31 Kevin Laeufer 0 0 0 8 18
32 Tynan McAuley 0 1 3 6 6
33 Daniel Resnick 0 0 0 10 10
33 Zachary Yedidia 0 0 0 10 10
33 jackbackrack 0 0 0 0 30
33 Palmer Dabbelt 0 0 0 0 30
37 Schuyler Eldridge 0 0 0 0 27
37 Andrew Lenharth 0 0 0 9 9
39 Paul Rigge 0 0 0 0 23
40 Jason Wang 0 2 2 2 2
Showing 21 to 40 of 150 results Previous Next
Contributing Companies

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