Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Computer Architecture
started in 2015
3,829 commits
154 contributors

Rank

1124 38

Git Repositories

Started

2015-04-27 3,747 days ago

GitHub Stars

4,156 #1,970

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 22 commits #1,293 6 contributors #1,058
Past 90 days 57 commits #1,453 12 contributors #1,091
Past 365 days 729 commits #888 37 contributors #1,025
Past 1095 days 1,811 commits #1,139 78 contributors #1,241
All time 3,829 commits 154 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
21 Mike Urbach
0 0 0 21 21
22 George
0 0 0 19 19
23 Albert Chen
0 0 0 17 17
24 Tynan McAuley
0 1 5 10 10
25 Kamyar Mohajerani
0 4 4 5 9
26 Henry Cook SiFive
0 0 0 0 45
26 qimingchu
0 0 6 9 9
28 Fabian Schuiki
0 0 6 8 8
29 Martin Schoeberl
0 0 2 7 21
30 Andrew Waterman
0 0 0 0 38
31 Albert Chen
0 0 0 11 15
32 Palmer Dabbelt
0 0 0 0 30
32 Daniel Resnick
0 0 0 10 10
32 jackbackrack
0 0 0 0 30
35 Andrew Lenharth
0 0 0 9 9
35 Schuyler Eldridge
0 0 0 0 27
37 Zachary Yedidia
0 0 0 8 10
37 Kevin Laeufer
0 0 0 4 18
39 edwardcwang
0 1 1 1 14
39 Paul Rigge
0 0 0 0 23
Showing 21 to 40 of 154 results
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Contributing Companies

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