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OSS Project

Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank
845
Increased by 66
Git Repositories
chisel3
Started
2015-04-27 3,557 days ago
Categories
Computer Architecture
GitHub Stars
4,090 #1,971
Stackoverflow Questions with tag chisel
694 #563
Weekly commits since inception
2015 2020 2025
Weekly contributors since inception
2015 2020 2025
Recent Project Activity
Day Span Commits Contributors
30 53 #675 9 #709
90 130 #970 17 #820
365 542 #1,118 41 #988
1095 1,484 #1,346 80 #1,245
All time 3,372 148
Contributing Individuals
Commits past X days
Contributor 30 90 All
1 Jack Koenig
SiFive
4 16 706
2 Schuyler Eldridge
SiFive
30 49 373
3 Chisel Bot 4 16 60
4 Jiuyang Liu 0 2 140
5 Jim Lawson
University of California, Berkeley
0 0 319
6 Andrew Waterman
SiFive
0 0 259
7 Megan Wachs 0 0 75
8 Aditya Naik 2 7 46
9 Will Dietz
SiFive
0 0 42
10 Ducky 0 0 199
11 Schuyler Eldridge 0 0 168
12 Chick Markley 0 0 110
13 unlsycn 3 12 15
14 Adam Izraelevitz 0 0 79
15 Sprite 2 2 23
16 Aditya Naik 0 10 18
17 Deborah Soung 0 0 32
18 Mike Urbach 0 0 20
19 qimingchu 5 5 8
20 Jared Barocsi 0 0 32
Contributing Companies

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