Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Computer Architecture
started in 2015
3,774 commits
152 contributors

Rank

820 2

Git Repositories

Started

2015-04-27 3,665 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 35 commits #1,025 11 contributors #656
Past 90 days 368 commits #501 17 contributors #864
Past 365 days 775 commits #849 37 contributors #1,036
Past 1095 days 1,816 commits #1,158 78 contributors #1,262
All time 3,774 commits 152 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
1 Schuyler Eldridge SiFive
1 253 349 599 635
2 Jack Koenig SiFive
10 62 207 510 782
3 Chisel Bot
5 13 50 77 77
4 Jim Lawson University of California, Berkeley
0 0 0 0 319
5 Jiuyang Liu
0 0 8 58 140
6 Andrew Waterman SiFive
0 0 0 2 259
7 Aditya Naik
3 5 19 44 51
8 Aditya Naik
8 9 19 27 27
9 Megan Wachs
0 0 8 56 76
10 Ducky
0 0 0 0 199
11 Schuyler Eldridge
0 0 0 0 168
12 Will Dietz SiFive
0 0 12 42 42
13 Chick Markley
0 0 0 22 110
14 unlsycn
2 3 20 20 20
15 Adam Izraelevitz
0 0 2 25 79
16 Deborah Soung
1 1 6 27 33
17 Trevor McKay
1 9 12 12 12
18 Jared Barocsi
0 0 0 29 32
19 Sprite
0 0 5 23 23
20 Mike Urbach
0 0 4 20 20
Showing 1 to 20 of 152 results
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Contributing Companies

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