Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank

868 4

Git Repositories

chisel3

Started

2015-04-27 3,589 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Past 30 days 63 commits #775 10 contributors #768
Past 90 days 162 commits #841 16 contributors #888
Past 365 days 541 commits #1,110 40 contributors #1,001
Past 1095 days 1,531 commits #1,316 78 contributors #1,267
All time 3,443 commits 148 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
1 Jack Koenig
SiFive
14 28 174 470 723
2 Schuyler Eldridge
SiFive
34 82 132 376 409
3 Chisel Bot 4 14 45 65 65
4 Jim Lawson
University of California, Berkeley
0 0 0 0 319
5 Jiuyang Liu 0 2 13 61 140
6 Andrew Waterman
SiFive
0 0 0 3 259
7 Megan Wachs 1 1 10 60 76
8 Aditya Naik 2 6 16 41 48
9 Will Dietz
SiFive
0 0 26 42 42
10 Ducky 0 0 0 0 199
11 Schuyler Eldridge 0 0 0 0 168
12 unlsycn 3 9 18 18 18
13 Chick Markley 0 0 0 23 110
14 Adam Izraelevitz 0 0 2 28 79
15 Sprite 0 2 15 23 23
16 Deborah Soung 0 0 7 26 32
17 Mike Urbach 0 0 11 20 20
18 Jared Barocsi 0 0 0 30 32
19 Aditya Naik 0 0 10 18 18
20 qimingchu 1 6 9 9 9
Showing 1 to 20 of 148 results Previous Next
Contributing Companies

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