Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Computer Architecture
started in 2015
3,823 commits
153 contributors

Rank

1033 43

Git Repositories

Started

2015-04-27 3,734 days ago

GitHub Stars

4,156 #1,970

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 21 commits #1,279 7 contributors #953
Past 90 days 70 commits #1,321 15 contributors #925
Past 365 days 744 commits #866 36 contributors #1,055
Past 1095 days 1,812 commits #1,140 77 contributors #1,256
All time 3,823 commits 153 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
1 Schuyler Eldridge SiFive
4 12 357 610 646
2 Jack Koenig SiFive
6 19 170 495 793
3 Chisel Bot
6 16 60 89 89
4 Jim Lawson University of California, Berkeley
0 0 0 0 319
5 Jiuyang Liu
0 0 6 56 140
6 Andrew Waterman SiFive
0 0 0 2 259
7 Aditya Naik
2 4 21 45 53
8 Ducky
0 0 0 0 199
9 Megan Wachs
0 0 2 49 76
10 Schuyler Eldridge
0 0 0 0 168
11 Will Dietz SiFive
0 0 10 42 42
12 Chick Markley
0 0 0 22 110
13 Adam Izraelevitz
1 1 3 24 80
14 Aditya Naik
0 0 19 27 27
15 unlsycn
0 2 20 20 20
16 Trevor McKay
0 4 16 16 16
17 Deborah Soung
0 1 5 26 33
18 Jared Barocsi
0 0 0 26 32
18 Sprite
0 0 5 23 23
20 Mike Urbach
0 0 4 20 20
Showing 1 to 20 of 153 results
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Contributing Companies

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