Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank

845 33

Git Repositories

chisel3

Started

2015-04-27 3,624 days ago

GitHub Stars

4,156 #1,972

Weekly commits since inception
2015 2020 2025

Weekly contributors since inception
2015 2020 2025

Recent Project Activity

Past 30 days 139 commits #432 7 contributors #1,023
Past 90 days 362 commits #505 15 contributors #961
Past 365 days 755 commits #884 38 contributors #1,053
Past 1095 days 1,776 commits #1,195 79 contributors #1,260
All time 3,703 commits 150 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
1 Schuyler Eldridge
SiFive
92 254 332 582 617
2 Jack Koenig
SiFive
39 64 207 508 766
3 Chisel Bot 3 11 45 69 69
4 Jim Lawson
University of California, Berkeley
0 0 0 0 319
5 Jiuyang Liu 0 0 13 61 140
6 Andrew Waterman
SiFive
0 0 0 2 259
7 Megan Wachs 0 1 10 57 76
8 Ducky 0 0 0 0 199
9 Aditya Naik 0 4 16 41 48
10 Will Dietz
SiFive
0 0 21 42 42
11 Schuyler Eldridge 0 0 0 0 168
12 Chick Markley 0 0 0 23 110
13 Adam Izraelevitz 0 0 2 27 79
14 unlsycn 0 6 18 18 18
15 Sprite 0 2 9 23 23
16 Deborah Soung 0 0 6 26 32
17 Jared Barocsi 0 0 0 29 32
18 Mike Urbach 0 0 8 20 20
18 Aditya Naik 0 0 10 18 18
20 qimingchu 0 6 9 9 9
Showing 1 to 20 of 150 results Previous Next
Contributing Companies

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