Sign up to vote
OSS Project

Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank
933
Decreased by 70
Git Repositories
chisel3
Started
2015-04-27 3,496 days ago
Categories
Computer Architecture
GitHub Stars
4,000 #1,974
Stackoverflow Questions with tag chisel
694 #563
Weekly commits since inception
2015 2019 2024
Weekly contributors since inception
2015 2019 2024
Recent Project Activity
Day Span Commits Contributors
30 25 #1,267 9 #826
90 130 #1,027 19 #790
365 526 #1,159 45 #906
1095 1,430 #1,386 79 #1,258
All time 3,267 147
Contributing Individuals
Commits past X days
Contributor 30 90 All
1 Jack Koenig
SiFive
5 61 695
2 Schuyler Eldridge
SiFive
3 13 327
3 Jiuyang Liu 0 4 138
4 Chisel Bot 5 12 49
5 Jim Lawson
University of California, Berkeley
0 0 319
6 Andrew Waterman
SiFive
0 0 259
7 Will Dietz
SiFive
0 8 42
8 Megan Wachs 0 1 75
9 Ducky 0 0 199
10 Aditya Naik 2 7 41
11 Schuyler Eldridge 0 0 168
12 Chick Markley 0 0 110
13 Adam Izraelevitz 0 2 79
14 Deborah Soung 0 3 32
15 Sprite 0 2 21
16 Mike Urbach 0 0 20
17 unlsycn 5 8 8
18 Jared Barocsi 0 0 32
19 Mike Urbach 0 0 21
20 George 0 0 19
Contributing Companies

Add this OSSRank shield to this project's README.md

[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1315)](https://ossrank.com/p/1315)