RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,181 commits
1,231 contributors

Rank

196 7

Started

2006-06-02 6,975 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 137 commits #350 24 contributors #298
Past 90 days 388 commits #442 56 contributors #252
Past 365 days 1,533 commits #500 178 contributors #216
Past 1095 days 6,996 commits #374 449 contributors #206
All time 25,181 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
805 Roman Elshin
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805 Robert Henry
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805 R. Steve McKown
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805 Richard Uhler
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805 sal
0 0 0 0 1
805 Santeri Salko
0 0 0 0 1
805 Stefan Arnold
0 0 0 0 1
805 Sylvain Chouleur
0 0 0 0 1
805 Sergio Chico
0 0 0 0 1
805 Simon Widmer
0 0 0 0 1
805 Simon Cook
0 0 0 0 1
805 Severin Junker
0 0 0 0 1
805 Sandeep Mistry
0 0 0 0 1
805 kevin
0 0 0 0 1
805 Alex Solomatnikov
0 0 0 0 1
805 Pawel Si
0 0 0 0 1
805 Stephen Tridgell
0 0 0 0 1
805 Steve Moorby
0 0 0 0 1
805 stkaplan
0 0 0 0 1
805 Bicheng Yang
0 0 0 0 1
Showing 1181 to 1200 of 1231 results
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Contributing Companies

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