RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,181 commits
1,231 contributors

Rank

196 7

Started

2006-06-02 6,975 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 137 commits #350 24 contributors #298
Past 90 days 388 commits #442 56 contributors #252
Past 365 days 1,533 commits #500 178 contributors #216
Past 1095 days 6,996 commits #374 449 contributors #206
All time 25,181 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
805 PoroCYon
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805 Prashanth Mundkur
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805 Premjith
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805 Pasquale Davide Schiavone
0 0 0 0 1
805 Purushothaman Palani
0 0 0 0 1
805 Rafael Calcada
0 0 0 0 1
805 Ragnar Sundblad
0 0 0 0 1
805 Rahul Masurkar
0 0 0 0 1
805 Ranjith Chandran
0 0 0 0 1
805 Tobias Diedrich
0 0 0 0 1
805 bob
0 0 0 0 1
805 Oleksandr Redchuk
0 0 0 0 1
805 Richard Barlow
0 0 0 0 1
805 Brandon Warhurst
0 0 0 0 1
805 rlrosa
0 0 0 0 1
805 roger
0 0 0 0 1
805 Romain Dolbeau
0 0 0 0 1
805 Roman Reichel
0 0 0 0 1
805 Rongcui Dong
0 0 0 0 1
805 Ronny Strutz
0 0 0 0 1
Showing 1161 to 1180 of 1231 results
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Contributing Companies

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