RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Rank

212 18

Started

2006-06-02 6,859 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent

GitHub Stars

8,179 #1,437

Weekly commits since inception

2006 2015 2025

Weekly contributors since inception

2006 2015 2025

Recent Project Activity

Past 30 days 84 commits #640 29 contributors #259
Past 90 days 279 commits #584 65 contributors #205
Past 365 days 1,714 commits #453 197 contributors #186
Past 1095 days 6,958 commits #380 451 contributors #205
All time 25,673 commits 1,234 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
816 Alex Murray 0 0 0 0 1
816 A.M 0 0 0 0 1
816 Andreas Loehre 0 0 0 0 1
816 Simon Johansson 0 0 0 0 1
816 Anders Westrup 0 0 0 0 1
816 Andrew Lyon 0 0 0 0 1
816 anpilog 0 0 0 0 1
816 Anton Kuzmin 0 0 0 0 1
816 Andrew 0 0 0 0 1
816 Ash Charles 0 0 0 0 1
816 Atish Patra 0 0 0 0 1
816 Ulrich-Lorenz Schlüter 0 0 0 0 1
816 Bartosz Bielawski 0 0 0 0 1
816 B. A. Bryce 0 0 0 0 1
816 Bernhard Kiesbauer 0 0 0 0 1
816 Bernhard Rosenkränzer 0 0 0 0 1
816 bluew 0 0 0 0 1
816 Jörg Mische 0 0 0 0 1
816 Stephane Bonnet 0 0 0 0 1
816 Boran Car 0 0 0 0 1
Showing 981 to 1000 of 1234 results Previous Next
Contributing Companies

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