RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,180 commits
1,231 contributors

Rank

194 1

Started

2006-06-02 6,973 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 146 commits #356 25 contributors #291
Past 90 days 397 commits #433 55 contributors #256
Past 365 days 1,540 commits #501 179 contributors #214
Past 1095 days 7,003 commits #374 449 contributors #206
All time 25,180 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
805 Ash Charles
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805 Atish Patra
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805 Ulrich-Lorenz Schlüter
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805 Bartosz Bielawski
0 0 0 0 1
805 B. A. Bryce
0 0 0 0 1
805 Bernhard Kiesbauer
0 0 0 0 1
805 Bernhard Rosenkränzer
0 0 0 0 1
805 bluew
0 0 0 0 1
805 Jörg Mische
0 0 0 0 1
805 Stephane Bonnet
0 0 0 0 1
805 Boran Car
0 0 0 0 1
805 Bradey Honsinger
0 0 0 0 1
805 Bruce Ableidinger
0 0 0 0 1
805 Bruno FLEURETTE
0 0 0 0 1
805 Byron Kubert
0 0 0 0 1
805 Chris Casinghino
0 0 0 0 1
805 Christopher Celio
0 0 0 0 1
805 Cheng-Shiun Tsai
0 0 0 0 1
805 Chin Huat Ang
0 0 0 0 1
805 Christopher Hoover
0 0 0 0 1
Showing 981 to 1000 of 1231 results
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Contributing Companies

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