RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Rank

225 34

Started

2006-06-02 6,859 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent

GitHub Stars

8,179 #1,437

Weekly commits since inception

2006 2015 2025

Weekly contributors since inception

2006 2015 2025

Recent Project Activity

Past 30 days 79 commits #677 26 contributors #298
Past 90 days 280 commits #583 64 contributors #210
Past 365 days 1,710 commits #453 198 contributors #187
Past 1095 days 6,961 commits #381 452 contributors #202
All time 25,677 commits 1,235 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
817 Boran Car 0 0 0 0 1
817 Bradey Honsinger 0 0 0 0 1
817 Bruce Ableidinger 0 0 0 0 1
817 Bruno FLEURETTE 0 0 0 0 1
817 Byron Kubert 0 0 0 0 1
817 Chris Casinghino 0 0 0 0 1
817 Cheng-Shiun Tsai 0 0 0 0 1
817 Chin Huat Ang 0 0 0 0 1
817 Christopher Hoover 0 0 0 0 1
817 Clément Burin des Roziers 0 0 0 0 1
817 Cristian Maglie 0 0 0 0 1
817 Colin Helliwell 0 0 0 0 1
817 Paul George 0 0 0 0 1
817 Marc Gauthier 0 0 0 0 1
817 Caleb Szalacinski 0 0 0 0 1
817 Andy Pomfret 0 0 0 0 1
817 Ryan Corbin 0 0 0 0 1
817 Daiane Angolini 0 0 0 0 1
817 Damyan Mitev 0 0 0 0 1
817 Daniel Trnka 0 0 0 0 1
Showing 1001 to 1020 of 1235 results Previous Next
Contributing Companies

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