RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Rank

212 19

Started

2006-06-02 6,858 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent

GitHub Stars

8,179 #1,437

Weekly commits since inception

2006 2015 2025

Weekly contributors since inception

2006 2015 2025

Recent Project Activity

Past 30 days 84 commits #642 29 contributors #262
Past 90 days 279 commits #585 65 contributors #205
Past 365 days 1,714 commits #452 197 contributors #186
Past 1095 days 6,958 commits #380 451 contributors #204
All time 25,673 commits 1,234 contributors

Contributing Individuals

Commits past X days
30 90 365 1095 All
816 lb5tr 0 0 0 0 1
816 Alexei Colin 0 0 0 0 1
816 Ilya Kharin 0 0 0 0 1
816 Michael Hope 0 0 0 0 1
816 Pushpal Sidhu 0 0 0 0 1
816 Alexandre Bourdiol 0 0 0 0 1
816 Fabio Utzig 0 0 0 0 1
816 Wealian Liao 0 0 0 0 1
816 Yueh-Ting (eop) Chen 0 0 0 0 1
816 Stephen L Arnold 0 0 0 0 1
816 Moritz 'Morty' Strübe 0 0 0 0 1
816 Ilia Motornyi 0 0 0 0 1
816 Stacey Sheldon 0 0 0 0 1
816 Jim Lin 0 0 0 0 1
816 Luis Marques 0 0 0 0 1
816 Marcythm 0 0 0 0 1
816 zhanghb97 0 0 0 0 1
816 Rupert Swarbrick 0 0 0 0 1
816 Simon Schubert 0 0 0 0 1
816 Benjamin Barenblat 0 0 0 0 1
Showing 921 to 940 of 1234 results Previous Next
Contributing Companies

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