RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,179 commits
1,231 contributors

Rank

195 1

Started

2006-06-02 6,972 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 147 commits #360 26 contributors #283
Past 90 days 395 commits #433 54 contributors #257
Past 365 days 1,541 commits #500 178 contributors #215
Past 1095 days 7,008 commits #374 450 contributors #206
All time 25,179 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
60 Menon, Nishanth
0 0 2 29 45
62 duane
0 0 0 0 105
63 Brian Campbell
0 2 4 8 68
64 Jan Matyas
0 0 0 20 63
64 Beeman Strong
2 3 12 15 15
66 kc8apf
0 0 0 0 94
66 Andrew Waterman
0 0 0 0 94
68 Léo Stefanesco
1 7 10 10 10
69 Prashanth Mundkur
0 3 13 13 13
69 Afonso Oliveira
0 0 15 15 15
71 jhauser-us
0 0 0 3 83
72 Andreas Faerber
0 0 0 0 87
73 Ian Thompson
0 0 1 27 28
74 guan jian
0 0 14 14 14
74 Jeff Scheel
0 0 0 28 28
76 Kevin-Andes
0 0 0 0 83
77 smatherd
0 7 9 9 9
78 mifi
0 0 0 0 80
79 Marek Vrbka
0 0 1 25 25
79 Farid Khaydari
0 0 13 13 13
Showing 61 to 80 of 1231 results
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Contributing Companies

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