RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,176 commits
1,231 contributors

Rank

195 1

Started

2006-06-02 6,972 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 147 commits #360 26 contributors #283
Past 90 days 395 commits #433 54 contributors #257
Past 365 days 1,541 commits #500 178 contributors #215
Past 1095 days 7,008 commits #374 450 contributors #206
All time 25,176 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
41 Alasdair
0 0 8 33 74
42 Jay Dev Jha
0 0 27 27 27
43 Nadime Barhoumi
3 11 17 17 17
44 Paul Donahue
0 0 7 24 91
45 Ved Shanbhogue
0 0 10 42 42
46 Daniel Anselmi
0 0 0 51 52
46 KotorinMinami
4 8 17 17 17
48 MingZhu Yan
2 10 17 17 17
49 Rafael Sene
0 0 7 43 43
50 Markku-Juhani O. Saarinen
0 1 2 10 117
51 Jan Matyas
0 0 17 31 31
52 ved-rivos
0 1 10 35 35
53 kdockser
0 0 3 43 43
54 Robert Norton
0 0 0 1 122
55 R. Diez
0 0 16 21 33
56 Neel Gala
0 0 0 23 73
57 Marc Schink
0 0 0 0 117
58 Mark Zhuang
0 1 12 24 24
59 Bill McSpadden
0 0 11 26 26
60 Menon, Nishanth
0 0 2 29 45
Showing 41 to 60 of 1231 results
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Contributing Companies

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