RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,865 commits
1,246 contributors

Rank

188 22

Started

2006-06-02 6,895 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 131 commits #428 31 contributors #247
Past 90 days 341 commits #543 62 contributors #235
Past 365 days 1,640 commits #466 191 contributors #198
Past 1095 days 6,984 commits #378 454 contributors #201
All time 25,865 commits 1,246 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
81 MingZhu Yan
2 4 8 8 8
82 Tsukasa OI
0 0 0 20 33
83 AndyGlew
0 0 0 0 72
84 Mathias K
0 0 0 0 71
85 Ahmed BOUDJELIDA
0 0 0 22 22
86 Radim Krčmář
1 3 8 8 8
87 Craig Topper SiFive
1 2 7 9 11
87 Leonard Anderweit
0 0 10 11 11
89 Stephano Cetola
0 0 0 7 47
90 Jon French
0 0 0 0 60
90 dbrownell
0 0 0 0 60
92 Colin Schmidt
0 0 0 0 58
93 Kirill Radkin
0 0 0 19 19
93 elisa
0 0 0 0 57
95 Salvador Arroyo
0 0 0 0 55
95 Yunsup Lee
0 0 0 0 55
95 Jessica Clarke
0 0 3 7 32
98 Nicolas Brunie
0 0 4 14 14
98 Marek
0 0 1 1 49
100 Tariq Kurd
0 0 0 17 17
Showing 81 to 100 of 1246 results
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Contributing Companies

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