RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,179 commits
1,231 contributors

Rank

194 1

Started

2006-06-02 6,973 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 146 commits #358 25 contributors #291
Past 90 days 397 commits #433 55 contributors #256
Past 365 days 1,540 commits #501 179 contributors #214
Past 1095 days 7,003 commits #374 449 contributors #206
All time 25,179 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
81 Mathias K
0 0 0 0 71
82 Radim Krčmář
1 2 9 9 9
83 Palmer Dabbelt
0 0 0 2 62
83 Ahmed BOUDJELIDA
0 0 0 22 22
85 Leonard Anderweit
0 0 10 11 11
86 dbrownell
0 0 0 0 60
86 Jon French
0 0 0 0 60
86 Marek
0 0 2 2 50
89 Tsukasa OI
0 0 0 13 33
90 Colin Schmidt
0 0 0 0 58
90 gfavor
3 3 3 5 12
92 Kirill Radkin
0 0 0 19 19
93 Salvador Arroyo
0 0 0 0 55
94 Nicolas Brunie
0 0 4 14 14
95 David Harris
0 4 6 6 6
96 Tariq Kurd
0 0 0 17 17
96 Jessica Clarke
0 0 2 7 31
98 mlu
0 0 0 0 49
98 Christopher Head
0 0 0 0 49
100 Craig Topper SiFive
0 0 7 9 9
Showing 81 to 100 of 1231 results
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Contributing Companies

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