RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,180 commits
1,231 contributors

Rank

202 1

Started

2006-06-02 6,974 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 145 commits #350 23 contributors #320
Past 90 days 395 commits #437 55 contributors #256
Past 365 days 1,537 commits #500 178 contributors #216
Past 1095 days 7,001 commits #374 449 contributors #206
All time 25,180 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
692 Brad Riensche
0 0 0 0 2
692 Brent Roman
0 0 0 0 2
692 bdwyatt
0 0 0 0 2
692 Tomek CEDRO
0 0 0 0 2
692 Chengyu Zheng
0 0 0 0 2
692 Christian Hoff
0 0 0 0 2
692 chuanhua
0 0 0 0 2
692 Marian Cingel
0 0 0 0 2
692 Andrew Leech
0 0 0 0 2
692 Dong Du
0 0 0 0 2
692 is2t
0 0 0 0 2
692 Dylan Reid
0 0 0 0 2
692 Dimitar Dimitrov
0 0 0 0 2
692 Dmitri Pavlov
0 0 0 0 2
692 Doug Brunner
0 0 0 0 2
692 Faisal Shah
0 0 0 0 2
692 Fraser Cormack
0 0 0 0 2
692 Gary Carlson
0 0 0 0 2
692 George Harris
0 0 0 0 2
692 daniel-k
0 0 0 0 2
Showing 741 to 760 of 1231 results
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Contributing Companies

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