RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,180 commits
1,231 contributors

Rank

203 1

Started

2006-06-02 6,973 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 145 commits #353 23 contributors #323
Past 90 days 395 commits #438 55 contributors #257
Past 365 days 1,537 commits #501 178 contributors #216
Past 1095 days 7,001 commits #374 449 contributors #206
All time 25,180 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
692 Grigory Okhotnikov
0 0 0 0 2
692 iosabi
0 0 0 0 2
692 Jon Burgess
0 0 0 0 2
692 John Pham
0 0 0 0 2
692 Kent Brinkley
0 0 0 0 2
692 Joakim Nohlgård
0 0 0 0 2
692 Johan Almquist
0 0 0 0 2
692 Kai Geissdoerfer
0 0 0 0 2
692 Bogdan Kolbov
0 0 0 0 2
692 Linus Tolke
0 0 0 0 2
692 Yun Liu
0 0 0 0 2
692 luca vinci
0 0 0 0 2
692 Marco Cruz
0 0 0 0 2
692 Martin Berger
0 0 0 0 2
692 mp-17
0 0 0 0 2
692 Mauro Gamba
0 0 0 0 2
692 Mikhail Rasputin
0 0 0 0 2
692 Mirko Vogt
0 0 0 0 2
692 Michele Sardo
0 0 0 0 2
692 sinan@isrc.iscas.ac.cn
0 0 0 0 2
Showing 761 to 780 of 1231 results
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Contributing Companies

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