OSS Project

RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Rank
232
Decreased by 35
Started
2006-06-02 6,752 days ago
Open Core Products
Open Core Company Product
efabless efabless
SiFive SiFive Core IP
Tenstorrent Grayskull
Ventana Micro Systems Ventana
GitHub Stars
7,861 #1,435
Stackoverflow Questions with tag riscv
1,411 #440
Weekly commits since inception
2006 2015 2024
Weekly contributors since inception
2006 2015 2024
Recent Project Activity
Day Span Commits Contributors
30 68 #682 25 #291
90 299 #570 56 #254
365 1,999 #394 192 #195
1095 7,060 #376 436 #216
All time 25,198 1,195
Contributing Individuals
Commits past X days
Contributor 30 90 All
680 Michele Sardo 0 0 2
680 Aleksey Shargalin 0 0 2
680 Jimmy 0 0 2
680 Olaf Lüke 0 0 2
680 Oleg Seiljus 0 0 2
680 Alex Crawford 0 0 2
680 Fujitsu FM3 Application Team 0 0 2
680 Owen Kirby 0 0 2
680 oyvind 0 0 2
680 Paul Richards 0 0 2
680 Peter D. Gray 0 0 2
680 Peter Dietzsch 0 0 2
680 Philip Nye 0 0 2
680 Po-wei Huang 0 0 2
680 Pushpal Sidhu 0 0 2
680 Rick Foos 0 0 2
680 Rohit Singh 0 0 2
680 Stian Skjelsad 0 0 2
680 Tomas Frydrych 0 0 2
680 Tommy Thorn 0 0 2
Contributing Companies

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