RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,181 commits
1,231 contributors

Rank

198 5

Started

2006-06-02 6,974 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 140 commits #354 24 contributors #300
Past 90 days 390 commits #441 56 contributors #252
Past 365 days 1,537 commits #500 178 contributors #216
Past 1095 days 6,999 commits #374 449 contributors #206
All time 25,181 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
692 Edward Forgacs
0 0 0 0 2
692 Daniel Glöckner
0 0 0 0 2
692 David Anders
0 0 0 0 2
692 Hans-Erik Floryd
0 0 0 0 2
692 Harald Welte
0 0 0 0 2
692 Ivo Manca
0 0 0 0 2
692 Lennert Buytenhek
0 0 0 0 2
692 Maxime COQUELIN
0 0 0 0 2
692 Michael Roth
0 0 0 0 2
692 Niklas Söderlund
0 0 0 0 2
692 Oleksandr Tymoshenko
0 0 0 0 2
692 Thomas Perrot
0 0 0 0 2
692 Tim Sander
0 0 0 0 2
692 Uwe Kleine-König
0 0 0 0 2
692 Yegor Yefremov
0 0 0 0 2
692 ksyx
0 0 0 0 2
692 Andreas Sandberg
0 0 0 0 2
692 Karl Palsson
0 0 0 0 2
692 Alexandru Gagniuc
0 0 0 0 2
692 Jae Hyun Yoo
0 0 0 0 2
Showing 701 to 720 of 1231 results
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Contributing Companies

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