RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,181 commits
1,231 contributors

Rank

196 7

Started

2006-06-02 6,975 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 140 commits #352 24 contributors #299
Past 90 days 390 commits #440 56 contributors #252
Past 365 days 1,537 commits #500 178 contributors #216
Past 1095 days 6,999 commits #374 449 contributors #206
All time 25,181 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
517 albert-azcarate
0 0 0 1 1
517 Guanghui Cheng
0 0 0 1 1
517 Guanghui Cheng
0 0 0 1 1
517 Paul Clarke
0 0 0 1 1
517 Bartosz Gasiorzewski
0 0 0 1 1
517 Riya Jain
0 0 0 1 1
517 sanket
0 0 0 1 1
517 Mark Featherston
0 0 0 1 1
517 Timur Golubovich
0 0 0 1 1
517 Jonathan Forrest
0 0 0 1 1
517 Karl Palsson
0 0 0 1 1
692 Jonathan Larmour
0 0 0 0 2
692 Alexander Stein
0 0 0 0 2
692 Alexandre TORGUE
0 0 0 0 2
692 Andrew Ruder
0 0 0 0 2
692 Jean-Christian de Rivaz
0 0 0 0 2
692 Jerome Forissier
0 0 0 0 2
692 Guido Guenther
0 0 0 0 2
692 Ewout ter Hoeven
0 0 0 0 2
692 Dongxue Zhang
0 0 0 0 2
Showing 681 to 700 of 1231 results
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Contributing Companies

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