RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,181 commits
1,231 contributors

Rank

196 7

Started

2006-06-02 6,975 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 137 commits #350 24 contributors #298
Past 90 days 388 commits #442 56 contributors #252
Past 365 days 1,533 commits #500 178 contributors #216
Past 1095 days 6,996 commits #374 449 contributors #206
All time 25,181 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
517 Abhinav Srivastava
0 0 0 1 1
517 mylai-mtk
0 0 0 1 1
517 akshaykumars614
0 0 0 1 1
517 splinedrive
0 0 0 1 1
517 OccupyMars2025
0 0 0 1 1
517 Yaksis
0 0 0 1 1
517 NaOHCC
0 0 0 1 1
517 Piotr Wegrzyn
0 0 0 1 1
517 Lucas
0 0 0 1 1
517 Steven Chang
0 0 0 1 1
517 Luca Rufer
0 0 0 1 1
517 SydMontague
0 0 0 1 1
517 wangyanwen
0 0 0 1 1
517 Alexander Richardson
0 0 0 1 1
517 Solra Bizna
0 0 0 1 1
517 Ioan-Cristian CÎRSTEA
0 0 0 1 1
517 Ioan-Cristian
0 0 0 1 1
517 Patrick Yingxi Pan
0 0 0 1 1
517 Aleksey Lotosh
0 0 0 1 1
517 Mudassir Ali
0 0 0 1 1
Showing 661 to 680 of 1231 results
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Contributing Companies

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