RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,176 commits
1,231 contributors

Rank

196 1

Started

2006-06-02 6,972 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 144 commits #366 26 contributors #280
Past 90 days 390 commits #440 54 contributors #258
Past 365 days 1,548 commits #493 177 contributors #219
Past 1095 days 7,001 commits #374 449 contributors #209
All time 25,176 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
21 zwelch
0 0 0 0 565
22 Evgeniy Naydanov
1 2 73 106 106
23 Oyvind Harboe
0 0 0 0 538
24 Marc Schink
0 0 37 101 224
25 David Brownell
0 0 0 0 531
26 Kersten Richter
0 3 23 125 125
27 Paul Fertser
0 0 2 11 407
28 Nicolas Brunie
0 0 6 130 130
29 Megan Wachs
0 0 0 0 398
30 ntfreak
0 0 0 0 324
31 Alper Ak
18 18 18 19 19
32 Andreas Fritiofson
0 0 0 1 252
33 Alex Richardson
0 2 23 42 42
34 Anatoly Parshintsev
0 0 21 45 45
35 Erhan Kurubas
0 0 0 56 80
36 Tarek BOCHKATI
0 0 0 4 179
37 Paul A. Clarke
5 13 15 20 20
38 Andreas Cord-Landwehr
0 0 0 59 59
39 Matthias Welwarsky
0 0 0 0 173
39 Alistair Francis
0 0 0 3 167
Showing 21 to 40 of 1231 results
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Contributing Companies

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