RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,176 commits
1,231 contributors

Rank

195 1

Started

2006-06-02 6,972 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 147 commits #360 26 contributors #283
Past 90 days 395 commits #433 54 contributors #257
Past 365 days 1,541 commits #500 178 contributors #215
Past 1095 days 7,008 commits #374 450 contributors #206
All time 25,176 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
1 Bill Traynor
7 20 71 1,718 1,736
2 Andrew Waterman SiFive
9 18 146 524 1,742
3 Tim Newsome SiFive
0 0 0 491 1,915
4 Antonio Borneo STMicroelectronics
0 0 91 366 1,263
5 Tim Hutt
32 58 143 185 185
6 Øyvind Harboe Ascenium
0 0 0 0 1,224
7 Krste Asanovic SiFive
0 0 0 82 987
8 Christian Herber
24 86 96 96 96
9 Prashanth Mundkur
16 31 45 45 530
10 Tariq Kurd Codasip
0 0 0 40 847
11 Ken Dockser Rivos
0 0 0 269 289
12 Jordan Carlin
8 36 101 111 111
13 Tomas Vanek
0 0 16 136 439
14 Dan Smathers Seagate
0 0 0 211 336
15 Ben Marshall PQShield
0 0 0 0 706
16 Khem Raj Comcast
1 3 13 101 371
17 Zach Welch
0 0 0 0 604
18 Spencer Oliver
0 0 0 0 603
19 Tim Newsome
0 0 32 162 164
20 Evgeniy Naydanov
0 3 42 143 143
Showing 1 to 20 of 1231 results
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Contributing Companies

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