RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,966 commits
1,251 contributors

Rank

195 12

Started

2006-06-02 6,913 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 105 commits #474 29 contributors #258
Past 90 days 363 commits #510 68 contributors #207
Past 365 days 1,599 commits #476 189 contributors #201
Past 1095 days 6,985 commits #375 451 contributors #205
All time 25,966 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
319 Ernie Edgar
0 0 0 0 8
319 Luca Bruno
0 0 0 0 8
319 Nathaniel Wesley Filardo
0 0 0 0 8
319 Angus Gratton
0 0 0 0 8
319 Atish Patra
0 0 0 0 8
319 Jian-Hong Pan
0 0 0 2 4
319 Simon Barner
0 0 0 0 8
319 Ake Rehnman
0 0 0 0 8
319 Bilal Sakhawat
0 0 0 1 6
319 sb-sf
0 0 0 0 8
331 Alexey Fisher
0 0 0 0 7
331 Yueh-Ting Chen
0 0 0 2 3
331 Han-Kuan Chen
0 0 0 0 7
331 Torbjørn Viem Ness
0 0 0 1 5
331 Craig Topper
0 0 0 2 3
331 Sunil V L
0 0 0 0 7
331 Robert Jarzmik
0 0 0 0 7
331 Jubilee Young TCDI
0 0 1 1 2
331 David Ung
0 0 0 0 7
331 Jim Paris
0 0 0 0 7
Showing 321 to 340 of 1251 results
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Contributing Companies

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