RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,191 commits
1,232 contributors

Rank

193 8

Started

2006-06-02 6,976 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 147 commits #353 25 contributors #299
Past 90 days 387 commits #441 55 contributors #251
Past 365 days 1,539 commits #500 179 contributors #217
Past 1095 days 7,004 commits #373 450 contributors #206
All time 25,191 commits 1,232 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
266 Kito Cheng SiFive
0 0 0 0 9
266 demin-han
0 0 1 2 2
266 Kamal Dasu
0 0 0 0 9
266 Alexandre Pereira da Silva
0 0 0 0 9
305 Ernie Edgar
0 0 0 0 8
305 Jian-Hong Pan
0 0 0 2 4
305 Peter A. Bigot
0 0 0 0 8
305 sb-sf
0 0 0 0 8
305 Nathaniel Wesley Filardo
0 0 0 0 8
305 Angus Gratton
0 0 0 0 8
305 Marc Pignat
0 0 0 0 8
305 Simon Barner
0 0 0 0 8
305 Ake Rehnman
0 0 0 0 8
305 Luca Bruno
0 0 0 0 8
305 Bilal Sakhawat
0 0 0 1 6
316 Craig Topper
0 0 0 2 3
316 Robert Jarzmik
0 0 0 0 7
316 Jubilee Young TCDI
0 0 1 1 2
316 David Ung
0 0 0 0 7
316 Jim Paris
0 0 0 0 7
Showing 301 to 320 of 1232 results
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Contributing Companies

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