RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,191 commits
1,232 contributors

Rank

194 6

Started

2006-06-02 6,976 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 147 commits #346 25 contributors #287
Past 90 days 387 commits #439 55 contributors #253
Past 365 days 1,539 commits #499 179 contributors #214
Past 1095 days 7,004 commits #372 450 contributors #205
All time 25,191 commits 1,232 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
336 Sevan Janiyan
0 0 0 2 2
336 Damjan Marion
0 0 0 0 6
336 Thomas Koeller
0 0 0 0 6
336 Thomas Gleinxer
0 0 0 1 4
336 Philipp Wagner IBM
0 0 0 0 6
336 Peter Mamonov
0 0 0 0 6
336 Matthijs Kooijman
0 0 0 2 2
336 Luke Lau
0 0 1 1 1
336 Julien Massot
0 0 0 0 6
336 Christian Eggers
0 0 0 0 6
336 Carl Friedrich Bolz-Tereick
0 0 1 1 1
336 Attila Kinali
0 0 0 0 6
336 François LEGAL
0 0 0 2 2
336 Eric Biggers
0 0 1 1 1
336 Alan Bowman
0 0 0 0 6
336 Alamy Liu
0 0 0 0 6
336 Akos Vandra
0 0 0 0 6
336 Patrick O'Neill
0 0 1 1 1
336 John Zaitseff
0 0 0 2 2
336 Lahfa Ryan
0 0 1 1 1
Showing 341 to 360 of 1232 results
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Contributing Companies

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