RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,983 commits
1,254 contributors

Rank

191 10

Started

2006-06-02 6,916 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 103 commits #488 29 contributors #253
Past 90 days 370 commits #498 70 contributors #205
Past 365 days 1,608 commits #471 189 contributors #201
Past 1095 days 6,974 commits #375 454 contributors #203
All time 25,983 commits 1,254 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
828 Roman Reichel
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828 Rongcui Dong
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828 Ronny Strutz
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828 Roman Elshin
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828 Robert Henry
0 0 0 0 1
828 R. Steve McKown
0 0 0 0 1
828 Richard Uhler
0 0 0 0 1
828 Sagar Karandikar
0 0 0 0 1
828 sal
0 0 0 0 1
828 Sandeep Rajendran
0 0 0 0 1
828 Santeri Salko
0 0 0 0 1
828 Stefan Arnold
0 0 0 0 1
828 Sylvain Chouleur
0 0 0 0 1
828 Sergio Chico
0 0 0 0 1
828 Simon Widmer
0 0 0 0 1
828 Simon Cook
0 0 0 0 1
828 Severin Junker
0 0 0 0 1
828 Sandeep Mistry
0 0 0 0 1
828 kevin
0 0 0 0 1
828 Alex Solomatnikov
0 0 0 0 1
Showing 1201 to 1220 of 1254 results
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Contributing Companies

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