RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,983 commits
1,254 contributors

Rank

189 9

Started

2006-06-02 6,916 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 103 commits #487 29 contributors #255
Past 90 days 370 commits #500 70 contributors #205
Past 365 days 1,608 commits #475 189 contributors #201
Past 1095 days 6,974 commits #375 454 contributors #203
All time 25,983 commits 1,254 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
828 Pawel Si
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828 Stephen Tridgell
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828 Steve Moorby
0 0 0 0 1
828 stkaplan
0 0 0 0 1
828 Bicheng Yang
0 0 0 0 1
828 Krzysztof Kajstura
0 0 0 0 1
828 Svetoslav Enchev
0 0 0 0 1
828 xuguangxiao
0 0 0 0 1
828 Takács Áron
0 0 0 0 1
828 mike brown
0 0 0 0 1
828 Thibaut Pérami
0 0 0 0 1
828 Thomas Søhus
0 0 0 0 1
828 Tobias Ringström
0 0 0 0 1
828 Tommy Vestermark
0 0 0 0 1
828 tymcauley
0 0 0 0 1
828 SASANO Takayoshi
0 0 0 0 1
828 Aymeric Vincent
0 0 0 0 1
828 EMARD
0 0 0 0 1
828 Yinan Xu
0 0 0 0 1
828 Yann Vernier
0 0 0 0 1
Showing 1221 to 1240 of 1254 results
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Contributing Companies

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