RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,983 commits
1,254 contributors

Rank

191 10

Started

2006-06-02 6,916 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 103 commits #490 29 contributors #254
Past 90 days 370 commits #499 70 contributors #205
Past 365 days 1,608 commits #472 189 contributors #202
Past 1095 days 6,974 commits #375 454 contributors #204
All time 25,983 commits 1,254 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
828 Dan Petrisko
0 0 0 0 1
828 Phil
0 0 0 0 1
828 Christoph Pittracher
0 0 0 0 1
828 PoroCYon
0 0 0 0 1
828 Prashanth Mundkur
0 0 0 0 1
828 Premjith
0 0 0 0 1
828 Pasquale Davide Schiavone
0 0 0 0 1
828 Purushothaman Palani
0 0 0 0 1
828 Rafael Calcada
0 0 0 0 1
828 Ragnar Sundblad
0 0 0 0 1
828 Rahul Masurkar
0 0 0 0 1
828 Ranjith Chandran
0 0 0 0 1
828 Tobias Diedrich
0 0 0 0 1
828 bob
0 0 0 0 1
828 Oleksandr Redchuk
0 0 0 0 1
828 Richard Barlow
0 0 0 0 1
828 Brandon Warhurst
0 0 0 0 1
828 rlrosa
0 0 0 0 1
828 roger
0 0 0 0 1
828 Romain Dolbeau
0 0 0 0 1
Showing 1181 to 1200 of 1254 results
Previous Next

Contributing Companies

Add the OSSRank badge to this project

OSSRank Badge Add this OSSRank shield to your project's README.md
[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1311)](https://ossrank.com/p/1311)