RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,955 commits
1,251 contributors

Rank

202 24

Started

2006-06-02 6,910 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 102 commits #501 27 contributors #279
Past 90 days 361 commits #524 66 contributors #213
Past 365 days 1,599 commits #477 189 contributors #202
Past 1095 days 6,979 commits #376 452 contributors #204
All time 25,955 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
826 Frans-Willem Hardijzer
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826 Gabor Csapo
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826 Greg Chadwick
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826 CezaryGapinski
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826 George Ioakimedes
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826 Gunnar Henne
0 0 0 0 1
826 Rene Kita
0 0 0 0 1
826 Nils Wistoff
0 0 0 0 1
826 Giuseppe Barba
0 0 0 0 1
826 vbx-glemieux
0 0 0 0 1
826 Guillaume Revaillot
0 0 0 0 1
826 Gabrielle Trotter
0 0 0 0 1
826 Zied Guermazi
0 0 0 0 1
826 Han Hartgers
0 0 0 0 1
826 Harald Kipp
0 0 0 0 1
826 HarishKumar
0 0 0 0 1
826 Henrik Nilsson
0 0 0 0 1
826 Heythem Bouhaja
0 0 0 0 1
826 Jan Vojtech
0 0 0 0 1
826 Hans Peter Mortensn
0 0 0 0 1
Showing 1061 to 1080 of 1251 results
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Contributing Companies

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