RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,972 commits
1,253 contributors

Rank

191 12

Started

2006-06-02 6,914 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 105 commits #480 30 contributors #246
Past 90 days 363 commits #514 70 contributors #205
Past 365 days 1,603 commits #476 191 contributors #198
Past 1095 days 6,991 commits #375 453 contributors #204
All time 25,972 commits 1,253 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
827 jihongbin
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827 Luis de Arquer
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827 Łukasz Misek
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827 Lu Yahan
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827 Ma_124
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827 Andrew MacIsaac
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827 Matthias Bock
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827 Laszlo Papp
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827 Johannes Stezenbach
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827 John David Anglin
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827 John Rigby
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827 John Szakmeister
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827 Jonathan Behrens
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827 Jonathan Tinkham
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827 Adrien Grassein
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827 Alberto García Hierro
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827 Aleksander Morgado
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827 Alexander Drozdov
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827 Alexey Brodkin
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827 Allen Martin
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Showing 1081 to 1100 of 1253 results
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Contributing Companies

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