RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,953 commits
1,251 contributors

Rank

197 13

Started

2006-06-02 6,910 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 108 commits #484 28 contributors #270
Past 90 days 359 commits #520 66 contributors #212
Past 365 days 1,601 commits #477 189 contributors #202
Past 1095 days 6,988 commits #376 452 contributors #204
All time 25,953 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
826 Laszlo Sitzer
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826 David Claffey
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826 dmitry pervushin
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826 Бурага Александр
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826 Thomas Eichinger
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826 Eldar Khayrullin
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826 Ravaz
0 0 0 0 1
826 Ethan Eade
0 0 0 0 1
826 Evan
0 0 0 0 1
826 lementec fabien
0 0 0 0 1
826 Felix Held
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826 fenugrec
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826 Ferdinand Postema
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826 Anthony Ferranti
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826 Flemming Futtrup
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826 Florian Meister
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826 Phil Fong
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826 Michael Brown
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826 Franck HÉRÉSON
0 0 0 0 1
826 Andrej Kazmin
0 0 0 0 1
Showing 1041 to 1060 of 1251 results
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Contributing Companies

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