RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,953 commits
1,251 contributors

Rank

197 13

Started

2006-06-02 6,909 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 108 commits #482 28 contributors #270
Past 90 days 359 commits #520 66 contributors #212
Past 365 days 1,601 commits #477 189 contributors #202
Past 1095 days 6,988 commits #376 452 contributors #204
All time 25,953 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
826 Clément Burin des Roziers
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826 Cristian Maglie
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826 fatalc
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826 Colin Helliwell
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826 Paul George
0 0 0 0 1
826 Marc Gauthier
0 0 0 0 1
826 Caleb Szalacinski
0 0 0 0 1
826 Andy Pomfret
0 0 0 0 1
826 Ryan Corbin
0 0 0 0 1
826 Daiane Angolini
0 0 0 0 1
826 Damyan Mitev
0 0 0 0 1
826 Daniel Trnka
0 0 0 0 1
826 Martin Nowak
0 0 0 0 1
826 Drew Barbier
0 0 0 0 1
826 David Brownell
0 0 0 0 1
826 ddraskovic
0 0 0 0 1
826 Denis Ivanov
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826 Dennis Ostermann
0 0 0 0 1
826 Rod Boyce
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826 DmitryShpak
0 0 0 0 1
Showing 1021 to 1040 of 1251 results
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Contributing Companies

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