RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,953 commits
1,251 contributors

Rank

196 13

Started

2006-06-02 6,909 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 108 commits #484 28 contributors #269
Past 90 days 359 commits #518 66 contributors #210
Past 365 days 1,601 commits #477 189 contributors #202
Past 1095 days 6,988 commits #376 452 contributors #203
All time 25,953 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
826 Andrew
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826 Ash Charles
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826 Atish Patra
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826 Ulrich-Lorenz Schlüter
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826 Bartosz Bielawski
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826 B. A. Bryce
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826 Bernhard Kiesbauer
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826 Bernhard Rosenkränzer
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826 bluew
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826 Jörg Mische
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826 Stephane Bonnet
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826 Boran Car
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826 Bradey Honsinger
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826 Bruce Ableidinger
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826 Bruno FLEURETTE
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826 Byron Kubert
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826 Chris Casinghino
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826 Cheng-Shiun Tsai
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826 Chin Huat Ang
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826 Christopher Hoover
0 0 0 0 1
Showing 1001 to 1020 of 1251 results
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Contributing Companies

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