RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,949 commits
1,251 contributors

Rank

194 12

Started

2006-06-02 6,909 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 113 commits #468 28 contributors #268
Past 90 days 355 commits #523 66 contributors #210
Past 365 days 1,616 commits #473 190 contributors #202
Past 1095 days 6,997 commits #375 453 contributors #203
All time 25,949 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
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826 Robbert
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826 kasperk81
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826 Sofia
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826 Anton Fedotov
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826 Adrian Burns
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826 Alexandre Joannou
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826 Andrew Kohlsmith
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826 Albert Ou
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826 Al Dyrius
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826 Alex Forencich
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826 Alex J Lennon
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826 Alex Murray
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826 A.M
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826 Andreas Loehre
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826 Simon Johansson
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826 Anders Westrup
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826 Andrew Lyon
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826 anpilog
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826 Anton Kuzmin
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Showing 981 to 1000 of 1251 results
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