RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,949 commits
1,251 contributors

Rank

192 15

Started

2006-06-02 6,908 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 113 commits #468 28 contributors #264
Past 90 days 355 commits #531 66 contributors #212
Past 365 days 1,616 commits #473 190 contributors #202
Past 1095 days 6,997 commits #375 453 contributors #203
All time 25,949 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
826 Arne Wichmann
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826 Jiří Pinkava
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826 Georg Sauthoff
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826 Philip Craig
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826 Vanya Sergeev
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826 Ncerzzk
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826 Zijian Zhang
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826 michael-roe
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826 Bartek Gąsiorzewski
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826 Rustem Yunusov
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826 eistar
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826 Arjan Bink
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826 Udit Khanna
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826 black-parrot
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826 billhuffman
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826 jhjung81
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826 ZL2WRW
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826 dave-estes-syzexion
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826 Wei-shan Wu
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826 Kai Meinhard
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Showing 961 to 980 of 1251 results
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Contributing Companies

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