RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,257 commits
1,238 contributors

Rank

216 18

Started

2006-06-02 6,997 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 81 commits #610 26 contributors #271
Past 90 days 378 commits #449 59 contributors #240
Past 365 days 1,492 commits #511 175 contributors #223
Past 1095 days 7,022 commits #370 447 contributors #210
All time 25,257 commits 1,238 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
692 sinan@isrc.iscas.ac.cn
0 0 0 0 2
692 Aleksey Shargalin
0 0 0 0 2
692 Jimmy
0 0 0 0 2
692 Olaf Lüke
0 0 0 0 2
692 Oleg Seiljus
0 0 0 0 2
692 Alex Crawford
0 0 0 0 2
692 Fujitsu FM3 Application Team
0 0 0 0 2
692 Owen Kirby
0 0 0 0 2
692 oyvind
0 0 0 0 2
692 Paul Richards
0 0 0 0 2
692 Peter D. Gray
0 0 0 0 2
692 Peter Dietzsch
0 0 0 0 2
692 Philip Nye
0 0 0 0 2
692 Po-wei Huang
0 0 0 0 2
692 Pushpal Sidhu
0 0 0 0 2
692 Rick Foos
0 0 0 0 2
692 Rohit Singh
0 0 0 0 2
692 Stephen Twigg
0 0 0 0 2
692 Stian Skjelsad
0 0 0 0 2
692 Tomas Frydrych
0 0 0 0 2
Showing 781 to 800 of 1238 results
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Contributing Companies

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