RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,937 commits
1,251 contributors

Rank

183 14

Started

2006-06-02 6,906 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 130 commits #408 30 contributors #240
Past 90 days 351 commits #530 69 contributors #204
Past 365 days 1,634 commits #464 192 contributors #197
Past 1095 days 7,003 commits #374 454 contributors #203
All time 25,937 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
711 George Harris
0 0 0 0 2
711 daniel-k
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711 Grigory Okhotnikov
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711 iosabi
0 0 0 0 2
711 Jon Burgess
0 0 0 0 2
711 John Pham
0 0 0 0 2
711 Kent Brinkley
0 0 0 0 2
711 Joakim Nohlgård
0 0 0 0 2
711 Johan Almquist
0 0 0 0 2
711 Kai Geissdoerfer
0 0 0 0 2
711 Bogdan Kolbov
0 0 0 0 2
711 Linus Tolke
0 0 0 0 2
711 Yun Liu
0 0 0 0 2
711 luca vinci
0 0 0 0 2
711 Marco Cruz
0 0 0 0 2
711 Martin Berger
0 0 0 0 2
711 mp-17
0 0 0 0 2
711 Mauro Gamba
0 0 0 0 2
711 Mikhail Rasputin
0 0 0 0 2
711 Mirko Vogt
0 0 0 0 2
Showing 781 to 800 of 1251 results
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Contributing Companies

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