RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,935 commits
1,251 contributors

Rank

182 15

Started

2006-06-02 6,906 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 129 commits #409 30 contributors #240
Past 90 days 357 commits #520 70 contributors #204
Past 365 days 1,640 commits #461 194 contributors #196
Past 1095 days 7,001 commits #375 454 contributors #203
All time 25,935 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
711 Ben Nahill
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711 Brad Riensche
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711 Brent Roman
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711 bdwyatt
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711 Tomek CEDRO
0 0 0 0 2
711 Christopher Celio
0 0 0 0 2
711 Chengyu Zheng
0 0 0 0 2
711 Christian Hoff
0 0 0 0 2
711 chuanhua
0 0 0 0 2
711 Marian Cingel
0 0 0 0 2
711 Andrew Leech
0 0 0 0 2
711 Dong Du
0 0 0 0 2
711 is2t
0 0 0 0 2
711 Dylan Reid
0 0 0 0 2
711 Dimitar Dimitrov
0 0 0 0 2
711 Dmitri Pavlov
0 0 0 0 2
711 Doug Brunner
0 0 0 0 2
711 Faisal Shah
0 0 0 0 2
711 Fraser Cormack
0 0 0 0 2
711 Gary Carlson
0 0 0 0 2
Showing 761 to 780 of 1251 results
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Contributing Companies

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