RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,257 commits
1,238 contributors

Rank

214 15

Started

2006-06-02 6,996 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 84 commits #580 26 contributors #275
Past 90 days 385 commits #443 59 contributors #240
Past 365 days 1,491 commits #510 174 contributors #224
Past 1095 days 7,020 commits #370 446 contributors #211
All time 25,257 commits 1,238 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
692 daniel-k
0 0 0 0 2
692 Grigory Okhotnikov
0 0 0 0 2
692 iosabi
0 0 0 0 2
692 Jon Burgess
0 0 0 0 2
692 John Pham
0 0 0 0 2
692 Kent Brinkley
0 0 0 0 2
692 Joakim Nohlgård
0 0 0 0 2
692 Johan Almquist
0 0 0 0 2
692 Kai Geissdoerfer
0 0 0 0 2
692 Bogdan Kolbov
0 0 0 0 2
692 Linus Tolke
0 0 0 0 2
692 Yun Liu
0 0 0 0 2
692 luca vinci
0 0 0 0 2
692 Marco Cruz
0 0 0 0 2
692 Martin Berger
0 0 0 0 2
692 mp-17
0 0 0 0 2
692 Mauro Gamba
0 0 0 0 2
692 Mikhail Rasputin
0 0 0 0 2
692 Mirko Vogt
0 0 0 0 2
692 Michele Sardo
0 0 0 0 2
Showing 761 to 780 of 1238 results
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Contributing Companies

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