RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,240 commits
1,237 contributors

Rank

212 15

Started

2006-06-02 6,993 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 91 commits #541 26 contributors #275
Past 90 days 373 commits #443 57 contributors #243
Past 365 days 1,477 commits #510 173 contributors #223
Past 1095 days 7,006 commits #372 446 contributors #210
All time 25,240 commits 1,237 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
61 duane
0 0 0 0 105
62 Jan Matyas
0 0 0 20 63
62 Menon, Nishanth
0 0 2 26 45
64 Bill McSpadden
0 0 7 26 26
65 Brian Campbell
0 0 4 8 68
66 kc8apf
0 0 0 0 94
66 Andrew Waterman
0 0 0 0 94
68 jhauser-us
0 0 0 3 83
69 Andreas Faerber
0 0 0 0 87
69 Afonso Oliveira
0 0 14 15 15
71 Prashanth Mundkur
0 2 13 13 13
72 Léo Stefanesco
0 6 10 10 10
72 guan jian
0 0 14 14 14
72 Jeff Scheel
0 0 0 28 28
75 Kevin-Andes
0 0 0 0 83
76 Ian Thompson
0 0 1 25 28
77 mifi
0 0 0 0 80
78 Farid Khaydari
0 0 13 13 13
78 Marek Vrbka
0 0 1 25 25
80 Mathias K
0 0 0 0 71
Showing 61 to 80 of 1237 results
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Contributing Companies

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