RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
26,111 commits
1,262 contributors

Rank

194 7

Started

2006-06-02 6,946 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 104 commits #478 27 contributors #259
Past 90 days 378 commits #467 65 contributors #218
Past 365 days 1,537 commits #489 181 contributors #209
Past 1095 days 7,014 commits #375 457 contributors #200
All time 26,111 commits 1,262 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
81 Beeman Strong
1 1 10 13 13
81 Marek Vrbka
0 0 1 25 25
83 Palmer Dabbelt
0 0 0 4 68
84 AndyGlew
0 0 0 0 72
84 David Harris
4 4 6 6 6
86 Mathias K
0 0 0 0 71
87 Ahmed BOUDJELIDA
0 0 0 22 22
88 Tsukasa OI
0 0 0 16 33
89 Leonard Anderweit
0 0 10 11 11
90 Jon French
0 0 0 0 60
90 dbrownell
0 0 0 0 60
90 Marek
0 0 2 2 50
93 Colin Schmidt
0 0 0 0 58
93 Craig Topper SiFive
0 2 7 9 11
95 elisa
0 0 0 0 57
95 Kirill Radkin
0 0 0 19 19
97 Yunsup Lee
0 0 0 0 55
97 Salvador Arroyo
0 0 0 0 55
97 Jessica Clarke
0 0 3 7 32
100 Nicolas Brunie
0 0 4 14 14
Showing 81 to 100 of 1262 results
Previous Next

Contributing Companies

Add the OSSRank badge to this project

OSSRank Badge Add this OSSRank shield to your project's README.md
[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1311)](https://ossrank.com/p/1311)