RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Rank

187 19

Git Repositories

riscv-openocd, riscv-isa-manual, riscv-debug-spec, riscv-crypto, sail-riscv, riscv-v-spec, riscv-code-size-reduction, meta-riscv, riscv-opcodes, riscv-fast-interrupt

Started

2006-06-02 6,893 days ago

Categories

Computer Architecture

Open Core Products

efabless efabless

SiFive Core IP SiFive

Grayskull Tenstorrent

Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception

2006

2015

2025

Weekly contributors since inception

2006

2015

2025

Recent Project Activity

Past 30 days	141 commits #408	31 contributors #251
Past 90 days	344 commits #536	63 contributors #230
Past 365 days	1,666 commits #459	192 contributors #197
Past 1095 days	6,981 commits #378	454 contributors #201
All time	25,855 commits	1,245 contributors

Contributing Individuals

	Commits past X days
	30	90	365	1095	All
81 AndyGlew	0	0	0	0	72
82 Mathias K	0	0	0	0	71
83 Nadime Barhoumi	2	6	6	6	6
84 MingZhu Yan	1	5	7	7	7
85 Ahmed BOUDJELIDA	0	0	0	22	22
86 Radim Krčmář	1	3	8	8	8
87 Craig Topper SiFive	1	2	7	9	11
87 Leonard Anderweit	0	0	10	11	11
89 Stephano Cetola	0	0	0	7	47
90 Jon French	0	0	0	0	60
90 dbrownell	0	0	0	0	60
92 Colin Schmidt	0	0	0	0	58
93 Kirill Radkin	0	0	0	19	19
93 elisa	0	0	0	0	57
95 Salvador Arroyo	0	0	0	0	55
95 Yunsup Lee	0	0	0	0	55
95 Jessica Clarke	0	0	3	7	32
98 Nicolas Brunie	0	0	4	14	14
98 Marek	0	0	1	1	49
100 Tariq Kurd	0	0	0	17	17

Showing 81 to 100 of 1245 results Previous Next

Contributing Companies

Toggle to view table

	Percentage of commits past X days
Contributing Companies	30	90	365	1095	All
SiFive	18%	11%	12%	18%	19%
STMicroelectronics	0%	1%	6%	6%	5%
Rivos	0%	0%	0%	4%	1%
Comcast	0%	0%	1%	2%	1%
Seagate	0%	0%	0%	3%	1%
Codasip	0%	0%	0%	1%	3%
Ascenium	0%	0%	0%	0%	5%
PQShield	0%	0%	0%	0%	3%

Add this OSSRank shield to this project's README.md

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