RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
26,111 commits
1,262 contributors

Rank

194 7

Started

2006-06-02 6,946 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 104 commits #480 27 contributors #259
Past 90 days 378 commits #468 65 contributors #218
Past 365 days 1,537 commits #489 181 contributors #209
Past 1095 days 7,014 commits #375 457 contributors #200
All time 26,111 commits 1,262 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
41 Paul Donahue
0 0 7 26 94
42 Nadime Barhoumi
6 13 14 14 14
43 Jay Dev Jha
0 0 27 27 27
44 Daniel Anselmi
0 0 0 51 52
45 Rafael Sene
0 0 8 43 43
46 ved-rivos
0 2 12 35 35
47 Markku-Juhani O. Saarinen
0 1 2 10 117
48 Jan Matyas
0 0 17 31 31
49 Paul A. Clarke
7 8 10 15 15
50 MingZhu Yan
3 9 15 15 15
51 kdockser
0 0 3 43 43
52 R. Diez
0 2 16 22 33
53 Philipp Tomsich
0 0 0 14 103
54 Neel Gala
0 0 0 27 73
55 Robert Norton
0 0 0 1 122
56 Marc Schink
0 0 0 0 117
57 David Kruckemyer Ventana Micro Systems
0 0 0 2 111
58 Prashanth Mundkur
0 9 13 13 13
59 Bill McSpadden
0 0 11 26 26
60 Menon, Nishanth
0 0 2 29 45
Showing 41 to 60 of 1262 results
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Contributing Companies

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