RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,237 commits
1,235 contributors

Rank

211 16

Started

2006-06-02 6,992 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 97 commits #518 25 contributors #286
Past 90 days 373 commits #441 55 contributors #249
Past 365 days 1,483 commits #510 174 contributors #224
Past 1095 days 7,009 commits #373 445 contributors #210
All time 25,237 commits 1,235 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
41 Alasdair
0 0 8 33 74
42 Paul Donahue
0 0 7 24 91
42 KotorinMinami
4 8 18 18 18
44 Daniel Anselmi
0 0 0 51 52
45 Jay Dev Jha
0 0 24 27 27
46 Paul A. Clarke
0 13 13 20 20
47 Rafael Sene
0 0 7 43 43
48 Markku-Juhani O. Saarinen
0 1 1 10 117
48 ved-rivos
1 1 9 36 36
48 Jan Matyas
0 0 17 31 31
51 kdockser
0 0 3 43 43
52 Ved Shanbhogue
0 0 2 42 42
53 MingZhu Yan
0 6 17 17 17
54 Robert Norton
0 0 0 1 122
55 R. Diez
0 0 16 21 33
56 Neel Gala
0 0 0 23 73
57 Marc Schink
0 0 0 0 117
58 Beeman Strong
2 4 13 16 16
59 Mark Zhuang
0 1 12 24 24
60 drath
0 0 0 0 109
Showing 41 to 60 of 1235 results
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Contributing Companies

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