RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,935 commits
1,251 contributors

Rank

183 14

Started

2006-06-02 6,906 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 129 commits #409 30 contributors #240
Past 90 days 357 commits #521 70 contributors #203
Past 365 days 1,640 commits #461 194 contributors #196
Past 1095 days 7,001 commits #375 454 contributors #203
All time 25,935 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
711 Gokturk Yuksek
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711 Luke Wren
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711 Jens Hoffmann
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711 Anton Kolesov
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711 Pavel Kirienko
0 0 0 0 2
711 Raúl Sánchez Siles
0 0 0 0 2
711 Roman D
0 0 0 0 2
711 Kevin Mills
0 0 0 0 2
711 VincentWu
0 0 0 0 2
711 Jaehoon Park
0 0 0 0 2
711 benscotstaveley
0 0 0 0 2
711 leahyao
0 0 0 0 2
711 Adam Bass
0 0 0 0 2
711 Ali Lown
0 0 0 0 2
711 Alex Ray
0 0 0 0 2
711 Andreas Bießmann
0 0 0 0 2
711 asier70
0 0 0 0 2
711 Austin Phillips
0 0 0 0 2
711 Andrew Wesie
0 0 0 0 2
711 Bas Vermeulen
0 0 0 0 2
Showing 741 to 760 of 1251 results
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Contributing Companies

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